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325A
CY7C1325A/GVT71256E18
256K x 18 Synchronous Flow-Through Burst SRAM
Features
* * * * * * * * * * * * * * * * Fast access times: 7.5 and 8 ns Fast clock speed: 117 and 100 MHz Provide high-performance 2-1-1-1 access rate Fast OE access times: 4.0 ns 3.3V -5% and +10% power supply 2.5V or 3.3V I/O supply 5V tolerant inputs except I/Os Clamp diodes to VSSQ at all inputs and outputs Common data inputs and data outputs Byte Write Enable and Global Write control Three chip enables for depth expansion and address pipeline Address, data and control registers Internally self-timed Write Cycle Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid Array) and 100-pin TQFP packages The CY7C1325A/GVT71256E18 SRAM integrates 262,144x18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (WEL, WEH, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE), and Sleep Mode Control (ZZ). The data outputs (DQ), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. WEL controls DQ1-DQ8 and DQP1. WEH controls DQ9-DQ16 and DQP2. WEL and WEH can be active only with BWE being LOW. GW being LOW causes all bytes to be written. The CY7C1325A/GVT71256E18 operates from a +3.3V power supply and all outputs operate on a +2.5V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. The device is ideally suited for 486, Pentium(R), 680x0, and PowerPCTM systems and for systems that benefit from a wide synchronous data bus.
Functional Description
The Cypress Synchronous Burst SRAM family employs highspeed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.
Selection Guide
7C1325A-117 71256E18-7 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA)
Pentium is a registered trademark of Intel Corporation. PowerPC is a trademark of IBM Corporation.
7C1325A-100 71256E18-8 8 320 10
7C1325A-100 71256E18-9 8 320 10
7C1325A-100 71256E18-10 8 320 10
7.5 370 10
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Document #: 38-05118 Rev. **
CA 95134 * 408-943-2600 Revised September 12, 2001
CY7C1325A/GVT71256E18
256K x 18 (CY7C1325A/GVT71256E18) Functional Block Diagram[1]
UPPER BYTE WRITE
WEH# BWE# CLK
D
Q
LOWER BYTE WRITE
WEL# GW# CE# CE2 CE2# ZZ OE# ADSP# Power Down Logic
D
Q
lo byte write hi byte write Output Buffers
ENABLE
D
Q
Input Register
A17-A2 ADSC#
Address Register 256K x 9 x 2 SRAM Array
CLR ADV# A1-A0 MODE Binary Counter & Logic
DQ1-DQ16 DQP1 DQP2
Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05118 Rev. **
Page 2 of 16
CY7C1325A/GVT71256E18
Pin Configurations
100-Pin TQFP Top View
A6 A7 CE CE2 NC NC WEH WEL CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 NC NC NC VCCQ VSSQ NC NC DQ9 DQ10 VSSQ VCCQ DQ11 DQ12 NC VCC NC VSS DQ13 DQ14 VCCQ VSSQ DQ15 DQ16 DQP2 NC VSSQ VCCQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1325A (256K X 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A10 NC NC VCCQ VSSQ NC DQP1 DQ8 DQ7 VSSQ VCCQ DQ6 DQ5 VSS NC VCC ZZ DQ4 DQ3 VCCQ VSSQ DQ2 DQ1 NC NC VSSQ VCCQ NC NC NC
Document #: 38-05118 Rev. **
MODE A5 A4 A3 A2 A1 A0 NC NC VSS VCC NC NC A15 A14 A13 A12 A11 A16 A17
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1325A/GVT71256E18
Pin Configurations (continued)
119-Ball Bump BGA 256Kx18--CY7C1325A/GVT71256E18 Top View
1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQ9 NC VCCQ NC DQ12 VCCQ NC DQ14 VCCQ DQ18 NC NC NC VCCQ 2 A6 CE2 A7 NC DQ10 NC DQ11 NC VCC DQ13 NC DQ15 NC DQP2 A5 A10 NC 3 A4 A3 A2 VSS VSS VSS BWH VSS NC VSS VSS VSS VSS VSS MODE A11 NC 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC NC NC 5 A8 A9 A12 VSS VSS VSS VSS VSS NC VSS BWL VSS VSS VSS NC A14 NC 6 A16 CE2 A15 DQ"P1 NC DQ7 NC DQ5 VCC NC DQ3 NC DQ2 NC A13 A17 NC 7 VCCQ NC NC NC DQ8 VCCQ DQ6 NC VCCQ DQ4 NC VCCQ NC DQ1 NC ZZ VCCQ
Pin Descriptions
BGA Pins QFP Pins Pin Name Type Description
4P, 4N, 2A, 3A, 37, 36, 35, 34, A0-A17 InputAddresses: These inputs are registered and must meet the set-up 5A, 6A, 3B, 5B, 33, 32, 100, 99, Synchronous and hold times around the rising edge of CLK. The burst counter 2C, 3C, 5C, 6C, 82, 81, 80, 48, generates internal addresses associated with A0 and A1, during 2R, 6R, 2T, 3T, 47, 46, 45, 44, burst cycle and wait cycle. 5T, 6T 49, 50 5L, 3G 93, 94 WEL, WEH InputByte Write Enables: A byte write enable is LOW for a Write cycle Synchronous and HIGH for a Read cycle. WEL controls DQ1-DQ8 and DQP1. WEH controls DQ9-DQ16 and DQP2. Data I/O are high-impedance if either of these inputs are LOW, conditioned by BWE being LOW. InputWrite Enable: This active LOW input gates byte write operations Synchronous and must meet the set-up and hold times around the rising edge of CLK. InputGlobal Write: This active LOW input allows a full 18-bit Write to Synchronous occur independent of the BWE and WEn lines and must meet the set-up and hold times around the rising edge of CLK. InputClock: This signal registers the addresses, data, chip enables, write Synchronous control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock's rising edge.
4M
87
BWE
4H
88
GW
4K
89
CLK
Document #: 38-05118 Rev. **
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CY7C1325A/GVT71256E18
Pin Descriptions (continued)
BGA Pins 4E 6B 2B 4F 4G QFP Pins 98 92 97 86 83 Pin Name CE CE2 CE2 OE ADV Type Description
InputChip Enable: This active LOW input is used to enable the device Synchronous and to gate ADSP. InputChip Enable: This active LOW input is used to enable the device. Synchronous inputChip Enable: This active HIGH input is used to enable the device. Synchronous Input Output Enable: This active LOW asynchronous input enables the data output drivers.
InputAddress Advance: This active LOW input is used to control the Synchronous internal burst counter. A HIGH on this pin generates wait cycle (no address advance). InputAddress Status Processor: This active LOW input, along with CE Synchronous being LOW, causes a new external address to be registered and a Read cycle is initiated using the new address. InputAddress Status Controller: This active LOW input causes device to Synchronous be deselected or selected along with new external address to be registered. A Read or Write cycle is initiated depending upon write control inputs. InputStatic InputAsynchronous Input/ Output Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst. Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). Data Inputs/Outputs: Low Byte is DQ1-DQ8. HIgh Byte is DQ9DQ16. Input data must meet setup and hold times around the rising edge of CLK. Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is parity bit for DQ9-DQ16. Power Supply: +3.3V -5% and +10% Ground: GND
4A
84
ADSP
4B
85
ADSC
3R
31
MODE
7T
64
ZZ
7P, 6N, 6L, 7K, 58, 59, 62, 63, 6H, 7G, 6F, 7E, 68, 69, 72, 73, 8, 1D, 2E, 2G, 1H, 9, 12, 13, 18, 19, 2K, 1L, 2M, 1N 22, 23 6D, 2P 4C, 2J, 4J, 6J, 4R 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 74, 24 15, 41,65, 91 17, 40, 67, 90
DQ1DQ16
DQP1, DQP2 VCC VSS
Input/ Output Supply Ground
1A, 7A, 1F, 7F, 4, 11, 20, 27, 54, 1J, 7J, 1M, 7M, 61, 70, 77 1U, 7U 5, 10, 21, 26, 55, 60, 71, 76 1B, 7B, 1C, 7C, 1-3, 6, 7, 14, 16, 2D, 4D, 7D, 1E, 25, 28-30, 38, 6E, 2F, 1G, 6G, 39, 42, 43, 512H, 7H, 3J, 5J, 53, 56, 57, 66, 1K, 6K, 2L, 4L, 75, 78, 79, 80, 7L, 6M, 2N, 7N, 95, 96 1P, 6P, 1R, 5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U
VCCQ
I/O Supply
Output Buffer Supply: +2.5V (from 2.375V to VCC)
VSSQ NC
I/O Ground -
Output Buffer Ground: GND No Connect: These signals are not internally connected.
Document #: 38-05118 Rev. **
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CY7C1325A/GVT71256E18
Burst Address Table (MODE = NC/VCC)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00
Burst Address Table (MODE = GND)
First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current
Current Current
CE H L L L L L L L L L X X H H X H X X H H
X H
CE2 X X H X H L L L L L X X X X X X X X X X
X X
CE2 X L X L X H H H H H X X X X X X X X X X
X X
ADSP X L L H H L L H H H H H X X H X H H X X
H X
ADSC L X X L L X X L L L H H H H H H H H H H
H H
ADV X X X X X X X X X X L L L L L L H H H H
H H
WRITE X X X X X X X L H H H H H H L L H H H H
L L
OE X X X X X L H X L H L H L H X X L H L H
X X
CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H
L-H L-H
DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z
D D
Notes: 2. X means "Don't Care." H means logic HIGH. L means logic LOW. WRITE = L means [BWE + WEL*WEH]*GW equals LOW. WRITE = H means [BWE + WEL*WEH]*GW equals HIGH. 3. WEL enables write to DQ1-DQ8 and DQP1. WEH enables write to DQ9-DQ16 and DQP2. 4. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 5. Suspending burst generates wait cycle. 6. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification
Document #: 38-05118 Rev. **
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CY7C1325A/GVT71256E18
Partial Truth Table for Read/Write
FUNCTION READ READ WRITE one byte WRITE all bytes WRITE all bytes GW H H H H L BWE H L L L X WEH X H L L X WEL X H H L X
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines only, not tested.) Voltage on VCC Supply Relative to VSS ..........-0.5V to +4.6V VIN ......................................................... -0.5V to +VCC+0.5V Storage Temperature (plastic) .................... -55C to +125C Junction Temperature ............................................... +125C Power Dissipation.......................................................... 1.4W Short Circuit Output Current ..................................... 100 mA
.
Operating Range
Range Com'l Ambient Temperature[9] 0C to +70C VCC 3.3V -5%/+10%
Electrical Characteristics Over the Operating Range[10]
Parameter VIHD VIH VIl ILI ILO VOH VOL VCC VCCQ Parameter ICC Input Low (Logic 0) Voltage[11, 12] 0V < VIN < VCC Output(s) disabled, 0V < VOUT < VCC IOH = -2.0 mA IOL = 2.0 mA 3.135 2.375 Input Leakage Current[13] Output Leakage Current Output High Output Low I/O Supply Voltage[11, 14] Voltage[11, 14] Description Input High (Logic 1) Voltage[11, 12] All other Test Conditions Data Inputs (DQxx) Min. 1.7 1.7 -0.3 -2 -2 1.7 0.7 3.6 VCC -1 50 MHz 200 Max. VCC+0.3 4.6 0.7 2 2 V V A A V V V V Unit
Supply Voltage[11]
Description Power Supply Current: Operating[15, 16, 17] CMOS Standby[16, 17]
Conditions Device selected; all inputs < VILor > VIH; cycle time > tKC Min.; VCC = Max.; outputs open Device deselected; VCC = Max.; all inputs < VSS + 0.2 or > VCC - 0.2; all inputs static; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; all inputs static; VCC = Max.; CLK frequency = 0 Device deselected; all inputs < VIL or > VIH; VCC = Max.; CLK cycle time > tKC Min.
-7 -8 Typ. 117 MHz 100 MHz 150 370 320
-9 90 MHz 290
Unit mA
ISB2
5
10
10
10
10
mA
ISB3
TTL Standby[16, 17]
10
20
20
20
20
mA
ISB4
Clock Running[16, 17]
40
80
70
60
40
mA
Notes: 9. TA is the case temperature. 10. Values in table are associated with the operating frequencies listed. 11. All voltages referenced to VSS (GND). 12. Overshoot: VIH < +6.0V for t < tKC /2. Undershoot: VIL < -2.0V for t < tKC /2. 13. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of 30 A. 14. AC I/O curves are available upon request. 15. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 16. "Device Deselected" means the device is in Power-Down mode as defined in the truth table. "Device Selected" means the device is active. 17. Typical values are measured at 3.3V, 25C and 20-ns cycle time.
Document #: 38-05118 Rev. **
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CY7C1325A/GVT71256E18
Thermal Consideration
Parameter JA JC Description Thermal Resistance - Junction to Ambient Thermal Resistance - Junction to Case Conditions Still air, soldered on 4.25 x 1.125 inch 4-layer PCB TQFP Typ. 25 9 Unit C/W C/W
Capacitance
Parameter CI CO Input Description Capacitance[18] Test Conditions TA = 25C, f = 1 MHz, VCC= 3.3V Typ. 4 7 Max. 5 8 Unit pF pF
Input/Output Capacitance (DQ)[18]
Typical Output Buffer Characteristics
Output High Voltage VOH (V) -0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 3.4 Pull-up Current IOH (mA) Min. -38 -38 -38 -26 -20 0 0 0 0 IOH (mA) Max. -105 -105 -105 -83 -70 -30 -10 0 0 Output Low Voltage VOL (V) -0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4 Pull-down Current IOL (mA) Min. 0 0 10 20 31 40 40 40 40 IL (mA) Max. 0 0 20 40 63 80 80 80 80
AC Test Loads and Waveforms
DQ Z0 = 50 2.5V RL = 50 Vt = 1.25V 10% 0V Rise Time: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time: 1 V/ns
Note: 18. This parameter is sampled.
Document #: 38-05118 Rev. **
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CY7C1325A/GVT71256E18
Switching Characteristics Over the Operating Range[19]
-7 117 MHz Parameter Clock tKC tKH tKL Clock Cycle Time Clock HIGH Time Clock LOW Time 8.5 3 3 10 4 4 11 4.5 4.5 20 4.5 4.5 ns ns ns Description Min. Max. -8 100 MHz Min. Max. -9 100 MHz Min. Max. -10 100 MHz Min. Max. Unit
Output Times tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z[18, 20, 21]
[18, 20, 21]
7.5 2 0 2 3.5 4.0 0 3.5 0 2 0 2
8 2 0 3.5 4.0 0 3.5 2
8.5 2 0 3.5 4.0 0 3.5 2
10
ns ns ns
Clock to Output in High-Z OE to Output Valid[22] OE to Output in
3.5 4.0
ns ns ns
Low-Z[18, 20, 21]
[18, 20, 21]
OE to Output in High-Z
3.5
ns
Set-Up Times tS Hold Times tH Address, Controls and Data In[23] 0.5 0.5 0.5 0.5 ns Address, Controls and Data In[23] 1.5 2.0 2.0 2.0 ns
Notes: 19. Test conditions as specified with the output loading as shown in AC Test Loads unless otherwise noted. Values in table are associated with the operating frequencies listed. 20. Output loading is specified with CL=5 pF as in AC Test Loads. 21. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 22. OE is a "Don't Care" when a byte write enable is sampled LOW. 23. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for "Don't Care" as defined in the truth table.
Document #: 38-05118 Rev. **
Page 9 of 16
CY7C1325A/GVT71256E18
Timing Diagrams
Read Timing[24]
t
KC
t
KL
CLK
t
S
t
KH
ADSP#
t
H
ADSC#
t
S
ADDRESS WEH#, WEL#, BWE#, GW# CE# (See Note)
A1
t
A2
H
t
S
ADV#
t
H
OE#
t t
KQ OELZ Q(A1)
t
t
OEQ Q(A2)
t
KQ Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Q(A2+2)
KQLZ
DQ
SINGLE READ
Note: 24. CE active in this timing diagram means that all Chip Enables CE, CE2, and CE2 are active.
BURST READ
Document #: 38-05118 Rev. **
Page 10 of 16
CY7C1325A/GVT71256E18
Timing Diagrams (continued)
Write Timing[24]
CLK
t
S
ADSP#
t
H
ADSC#
t
S
ADDRESS WEH#, WEL#, BWE# GW# CE# (See Note)
A1
tH
A2
A3
t
S
ADV#
t
H
OE#
t t
OEHZ
KQX Q D(A1) D(A2) D(A2+2) D(A2+2) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)
DQ
SINGLE WRITE
BURST WRITE
BURST WRITE
Document #: 38-05118 Rev. **
Page 11 of 16
CY7C1325A/GVT71256E18
Timing Diagrams (continued)
Read/Write Timing[24]
CLK
t
S
ADSP#
t
H
ADSC#
t
S
ADDRESS WEH#, WEL#, BWE#, GW# CE# (See Note) ADV#
A1
A2
t
A3
H
A4
A5
OE#
DQ
Q(A1)
Q(A2)
D(A3) Single Write
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
D(A5)
D(A5+1)
Single Reads
Burst Read
Burst Write
Document #: 38-05118 Rev. **
Page 12 of 16
CY7C1325A/GVT71256E18
Ordering Information
Speed (MHz) 117 Ordering Code CY7C1325A-117AC GVT71256E18T-7 CY7C1325A-117BGC GVT71256E18B-7 100 CY7C1325A-100AC GVT71256E18T-8 CY7C1325A-100BGC GVT71256E18B-8 100 CY7C1325A-100AC GVT71256E18T-9 CY7C1325A-100BGC GVT71256E18B-9 100 CY7C1325A-100AC GVT71256E18T-10 CY7C1325A-100BGC GVT71256E18B-10 BG119 119-Lead FBGA (14 x 22 x 2.4 mm) A101 100-Lead Thin Quad Flat Pack Commercial BG119 119-Lead FBGA (14 x 22 x 2.4 mm) A101 100-Lead Thin Quad Flat Pack Commercial BG119 119-Lead FBGA (14 x 22 x 2.4 mm) A101 100-Lead Thin Quad Flat Pack Commercial BG119 119-Lead FBGA (14 x 22 x 2.4 mm) Package Name A101 Package Type 100-Lead Thin Quad Flat Pack Operating Range Commercial
Document #: 38-05118 Rev. **
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CY7C1325A/GVT71256E18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05118 Rev. **
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CY7C1325A/GVT71256E18
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-05118 Rev. **
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CY7C1325A/GVT71256E18
Document Title: CY7C1325A/GVT71256E18 256K x 18 Synchronous Flow-Through Burst SRAM Document Number: 38-05118 REV. ** ECN NO. 108298 Issue Date 09/25/01 Orig. of Change BRI Description of Change New Cypress spec--converted from Galvantech format
Document #: 38-05118 Rev. **
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